1. Field
The disclosed embodiments generally relate to techniques for improving performance in computer systems. More specifically, the disclosed embodiments relate to the design of an adaptive prefetcher that dynamically adjusts the aggressiveness of the prefetches it generates based on observed memory access patterns in a preceding time window.
2. Related Art
As the gap between processor performance and memory performance continues to grow, prefetching is becoming an increasingly important technique for improving computer system performance. Prefetching involves issuing special “prefetch instructions” to retrieve cache lines into a cache before the cache lines are actually accessed by an application. This prevents the application from having to wait for a cache line to be retrieved from memory and thereby improves computer system performance. Stride prefetchers are commonly used to prefetch a sequence of data references having a constant stride. Unfortunately, existing stride prefetchers are often too aggressive, attempting to prefetch too far ahead and issuing too many prefetches, particularly when the computer system is running in a throughput-oriented mode. Empirical results indicate that reducing prefetcher aggressiveness can result in better bandwidth utilization and better overall performance for various workloads.
However, no single prefetcher configuration works well for all workloads. Hence, using a single prefetching configuration often leads to bandwidth wastage and performance loss, especially when the system is operating in a throughput-oriented mode.